A conventional six-bit flash A/D converter employs an array of 63 comparators and 63 latches. Known ways to reduce this complexity are multi-step, folding and interpolation techniques.
The multi-step approach uses two or more low resolution converters in a pipeline arrangement. This results in a dramatic reduction in the number of comparators. However, one requirement of this architecture is that the decision bits from one step must be made available in a timely fashion for use by the next step. Tolerance to errors can be built into this decision using redundancy, however a complete decision must still be made. This can be a problem at high speeds because of potential metastability. In a single-step flash A/D converter, stability problems can be overcome by providing additional latches at the outputs of the comparators. However, this cannot be done in a multi-step pipeline converter.
The folding technique involves folding the input several times to map different regions of the input into a single output range. It would be ideal to use a single such folder and then subject the folded signal to a low resolution flash conversion. For instance, if a signal could be folded eight times, three bits could be realized out of this operation itself. Then, only a three-bit flash conversion would be required following the folder. Unfortunately, the folding operation introduces nonlinearity except in the vicinity of the zero crossing of the output. For this reason, practical folding A/D converters use multiple folders that are offset from each other, with the net result that there are so many folded signals that each signal must be linear only over one least significant bit (LSB). Thus, folding by itself does not result in a reduction in the number of input devices or the input capacitance, but only results in a reduction in the number of latches and simplifies the encoder.
Interpolation can be applied to any flash A/D converter, with or without folding. In the simplest form of implementation of interpolation, a six-bit converter uses only 32 input preamplifiers with their reference voltages spaced two LSBs apart. By interpolating (or averaging) between adjacent preamplifier outputs, 32 more signals can be derived that actually represent virtual preamplifier outputs for the other 32 reference levels that were skipped.
A combination of folding and interpolation has been employed in several recent implementations. However, all of these have the drawback that the folding does not reduce the number of input stages or the total input capacitance.